TIMER0: 8-bit timer/counter (TCNT0)

 http://www.filosofisica.com/classes/uproc/material/timers_AVR.html

 

The counter can be clocked internally or externally through T0 pin (PD4, Arduino 4). When clocked internally, the clock is passed through a configurable prescaler. This is configured using the CS02:0 (Clock Select) bits on the TCCR0B (Timer/Counter Control Register).

TCCR0B (Timer/Counter Control Reg. B)
7	FOC0A	Force Output Compare A
6	FOC0B	Force Output Compare B
5	--
4	--
3	WGM02	Waveform Generation Mode
2	CS02	Clock Select
1	CS01
0	CS00

CS02:0	Clock Selection
000	Timer/Counter stopped
001	Internal Clock clkI/O
010	Internal Clock clkI/O divided by 8
011	Internal Clock clkI/O divided by 64
100	Internal Clock clkI/O divided by 256
101	Internal Clock clkI/O divided by 1024
110	External clock on falling edge of T0 pin (PD4, Arduino 4)
111	External clock on rising edge of T0 pin

 This counter has four modes of operation configurable through WGM02:0 bits on the TCCR0x registers. In the normal mode, the counter always counts up and restarts from 0x00 when it reaches 0xFF.

TCCR0A (Timer/Counter Control Reg. A)
7	COM0A1	Compare Match Output A Mode
6	COM0A0
5	COM0B1	Compare Match Output B Mode
4	COM0B0
3	--
2	--
1	WGM01	Waveform Generation Mode
0	WGM00

WGM2:0	Operation Mode	TOP	Update of OCRx at	TOV0 set on
000	Normal	0xFF	Immediate	0xFF
010	CTC	OCRA	Immediate	0xFF

When the counter overflows, TOV0 (Timer/Counter Overflow Flag) is set.

TIFR0 (Timer/Counter Interrupt Flag Register)
7	--
6	--
5	--
4	--
3	--
2	OCF0B	Timer/Counter 0 Output Compare B Match Flag
1	OCF0A	Timer/Counter 0 Output Compare A Match Flag
0	TOV0	Timer/Counter 0 Overflow Flag

 The second mode of operation is called Clear Timer on Compare Match (CTC). In this mode, the counter is cleared when TCNT0 matches the value stored in OCR0A. It is possible to generate a waveform on the OC0A pin (PD6, Arduino 6) using this mode by configuring  COM0A1:0 bits on TCCR0A.

COM0A1:0	Description
00	OC0A disconnected
01	Toggle OC0A on compare match
10	Clear OC0A on compare match
11	Set OC0A on compare match

 The waveform frequency is given by:

where N is the prescale factor (1, 8, 64, 256 or 1024). Therefore, for a clock of 4MHz, the shortest period of operation is 0.5 us (2 MHz) for N = 1, OCRnx = 0 and the longest period is 0.13 s (7.63 Hz) for N = 1024, OCRnx = 255.

 When the counter register TCNT0 overflows, an interrupt can be generated by configuring the TIMSK0 register.

TIMSK0 (Timer/Counter Interrupt Mask)
7	--
6	--
5	--
4	--
3	--
2	OCIE0B	Timer/Counter 0 Output Compare Match B Interrupt Enable
1	OCIE0A	Timer/Counter 0 Output Compare Match A Interrupt Enable
0	TOIE0	Timer/Counter 0 Overflow Interrupt Enable

The corresponding interrupt vectors are:

Address	Interrupt
0x001C	Timer/Counter 0 compare match A
0x001E	Timer/Counter 0 compare match B
0x0020	Timer/Counter 0 overflow

EXAMPLE Init_Timer:  clr R16  ; Initialize counter  out TCNT0,R16  ldi R16,(1<<COM0A0)  ; Toggle OC0A and CTC on OCRA  ori R16,(1<<WGM01)  out TCCR0A,R16    ldi R16,(1<<CS02)  ; Set prescaler to 1:1024  ori R16,(1<<CS00)    out TCCR0B,R16  ldi R16,value ; Value to be compared  out OCR0A,R16  sei  ; Enable interrupts if needed

TIMER1: 16-bit timer/counter (TCNT1)

  As with the previous timer, Timer1 has a prescaler too. This can be configured through bits CS12:0 on TCCR1B (Timer/Counter 1 Control Register B) register.

TCCR1B (Timer/Counter Control Register B)
7	ICNC1	Input Capture Noice Canceler
6	ICES1	Input Capture Edge Select
5	--
4	WGM13	Wavefrom Generation Mode
3	WGM12
2	CS12	Clock Select
1	CS11
0	CS10

CS12:0	Clock Selection
000	Timer/Counter stopped
001	Internal Clock clkI/O
010	Internal Clock clkI/O divided by 8
011	Internal Clock clkI/O divided by 64
100	Internal Clock clkI/O divided by 256
101	Internal Clock clkI/O divided by 1024
110	External clock on falling edge of T1 pin (PD5, Arduino 5)
111	External clock on rising edge of T1 pin

 The operation mode is selected through the WGM13:0 bits.

TCCR1A (Timer/Counter Control Register A)
7	COM1A1	Compare Output Mode for Channel A
6	COM1A0
5	COM1B1	Compare Output Mode for Channel B
4	COM1B0
3	--
2	--
1	WGM11	Waveform Generation Mode
0	WGM10

WGM	Mode	TOP	Update OCR1x at	Set TOV1 on
0000	Normal	0xFFFF	Immediate	0xFFFF
0100	CTC	OCR1A	Immediate	0xFFFF
1100	CTC	ICR1	Immediate	0xFFFF

 ICR1 can be updated with TCNT1 every time an event happens in ICP1 (PB0, Arduino 8). This can be used to produce a time stamp of an event. When this happens, the flag ICF1 is raised. The input can be digitally filtered by setting the bit TCCR1B:ICNC1 (Input Capture Noise Canceler). The edge at which the trigger is executed is configured through bit TCCR1B:ICES1 (Input Capture Edge Select), 0 selects falling edge whereas 1 selects raising edge.

 It can also be used to generate a waveform on OC1A/OC1B (PB1/2, Arduino 9/10) through COM1x1:0 bits.

COM1A1:0/COM1B1:0	Description
00	OC1A/OC1B (PB1/PB2, Arduino 9/10) disconnected
01	Toggle OC1A/OC1B on compare match
10	Clear OC1A/OC1B on compare match
11	Set OC1A/OC1B on compare match

 In CTC mode, the value of TCNT1 is compared with OCR1A or ICR1 (Input Capture Register) depending on the configuration of the WGM bits. When overflow is produced, a corresponding flag is raised.

TIFR1 (Timer/Counter Interrupt Flag Register)
7	--
6	--
5	ICF1	Timer/Counter 1 Input Capture Flag
4	--
3	--
2	OCF1B	Timer/Counter 1 Output Compare B Match Flag
1	OCF1A	Timer/Counter 1 Output Compare A Match Flag
0	TOV1	Timer/Counter 1 Overflow Flag

 When the counter register TCNT1 overflows, an interrupt can be generated by configuring the TIMSK1 register.

TIMSK1 (Timer/Counter Interrupt Mask)
7	--
6	--
5	ICIE1	Timer/Counter 1 Input Capture Interrupt Enable
4	--
3	--
2	OCIE1B	Timer/Counter 1 Output Compare Match B Interrupt Enable
1	OCIE1A	Timer/Counter 1 Output Compare Match A Interrupt Enable
0	TOIE1	Timer/Counter 1 Overflow Interrupt Enable

 The corresponding interrupt vectors are:

Address	Interrupt
0x0014	Timer/Counter 1 capture event
0x0016	Timer/Counter 1 compare match A
0x0018	Timer/Counter 1 compare match B
0x001A	Timer/Counter 1 overflow

 The main advantage of using 16 bits is that we can achieve longer periods. For a clock of 4 MHz, the shortest period of operation still is 0.5 us (2 MHz) for N = 1, OCRnx = 0 but the longest period is 33.55 s (0.03 Hz) for N = 1024, OCRnx = 65535. For example, a period of 20 ms can be achieved by setting N = 8 and OCR = 4999.

 In an Arduino Uno board, the clock is 16 MHz. Therefore, for a period of 1 s, one can set the prescaler to 256 and OCR to 31249.

TIMER2: 8-bit timer/counter (TCNT2)

 This counter is very similar to TIMER0 but it also has an asynchronous operation. The prescaler is configured through CS22:0 bits.

TCCR2B (Timer/Counter Control Reg. B)
7	FOC2A	Force Output Compare A
6	FOC2B	Force Output Compare B
5	--
4	--
3	WGM22	Waveform Generation Mode
2	CS22	Clock Select
1	CS21
0	CS20

CS22:0	Clock Selection
000	Timer/Counter stopped
001	Internal Clock clkI/O
010	Clock clkT2S divided by 8
011	Clock clkT2S divided by 32
100	Clock clkT2S divided by 64
101	Clock clkT2S divided by 128
110	Clock clkT2S divided by 256
111	Clock clkT2S divided by 1024

The mode of operation is configured through WGM2xn on TCCR2A.

TCCR2A (Timer/Counter Control Register A)
7	COM2A1	Compare Output Mode for Channel A
6	COM2A0
5	COM2B1	Compare Output Mode for Channel B
4	COM2B0
3	--
2	--
1	WGM21	Waveform Generation Mode
0	WGM20

WGM22:0	Mode of Operation	TOP	Update OCRx at	Set TOV Flag on
000	Normal	0xFF	Immediate	0xFF
010	CTC	OCRA	Immediate	0xFF

 When overflow or matching with OCR2A/B occur, corresponding flags are raised.

TIFR2 (Timer/Counter Interrupt Flag)
7	--
6	--
5	--
4	--
3	--
2	OCF2B	Output Compare Flag 2 B
1	OCF2A	Output Compare Flag 2 A
0	TOV2	Timer/Counter 2 Overflow Flag

 The comparations and overflow can generate interrupt signals that can be enabled through TIMSK2 register.

TIMSK2 (Timer/Counter Interrupt Mask)
7	--
6	--
5	--
4	--
3	--
2	OCIE2B	Timer/Counter 1 Output Compare Match B Interrupt Enable
1	OCIE2A	Timer/Counter 1 Output Compare Match A Interrupt Enable
0	TOIE2	Timer/Counter 1 Overflow Interrupt Enable

 The corresponding interrupt vectors are:

Address	Interrupt Source
0x000E	Timer/Counter2 compare match A
0x0010	Timer/Counter2 compare match B
0x0012	Timer/Counter2 overflow

 The asynchronous operation is set by the ASSR (Asynchronous Status) Register.

ASSR (Asynchronous Status Register)
7	--
6	EXCLK	Enable External Clock Input on TOSC1 pin (PB6)
5	AS2	Asynchronous Timer/Counter 2 is clocked from TOSC1
4	TCN2UB	Timer/Counter 2 Update Busy (R)
3	OCR2AUB	Output Compare Register 2 Update on OCR2A Busy (R)
2	OCR2BUB	Output Compare Register 2 Update on OCR2B Busy (R)
1	TCR2AUB	Timer/Counter Control Reg. 2 Update on TCCR2A Busy (R)
0	TCR2BUB	Timer/Counter Control Reg. 2 Update on TCCR2B Busy (R)